nine-output, 200-mh z zero delay buff er cy2309 a cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07378 rev. *b revised march 5, 2003 features ? 50-mhz to 200-mhz operating range 650-ps max. total timing budget? (ttb?) window nine low-skew outputs, grouped as 4 + 4 + 1 ? output-output skew < 200 ps ? device-device skew < 500 ps input-output skew < 250 ps cycle-cycle jitter < 100 ps three-stateable outputs < 50- a shutdown current spread aware? phase-locked loop (pll) bypass mode (see table 1 ) 16-pin tssop 3.3v operation commercial/industrial temperature description the cy2309a is a high-performance 200-mhz zero delay buffer designed for high-speed clock distribution. the integrated pll is designed for low jitter and optimized for noise rejection. these parameters are critical for reference clock distribution in systems using high-performance asics and microprocessors. the cy2309a pll feedback is internal and is connected to clkout. the device features a guaranteed maximum ttb window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. the cy2309a has two banks of four outputs each, which can be controlled by the select inputs as shown in table 1 . if all the output clocks are not required, bank b can be three-stated. the select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes (pll bypass mode). the cy2309a pll enters a power-down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off, resulting in less than 50 a of current draw. the pll shuts down in two additional cases, as shown in table 1 . the cy2309a is available in standard (?1) or high-drive (?1h) output versions. the high-drive features faster rise and fall times. block diagram pin configuration clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 clkout s2 s1 select input decoding mux ref pll 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ref clkb1 clkb2 v dd gnd clkb3 clkb4 s2 clkout clka1 clka2 v dd gnd clka3 clka4 s1 tssop top view
cy2309 a document #: 38-07378 rev. *b page 2 of 9 zero delay and skew control since the clkout is the internal feedback to the pll, its relative loading can adjust the input-output delay. see figure 1 for applications requiring zero input-output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. if input-output delay adjustments are required, use the above graph to calculate loading differences between the clkout and other outputs. for zero output-output skew, be sure to load all outputs equally. for further information on using cy2309a, refer to the application note ?cy2309 as pci and sdram buffers.? notes: 1. weak pull-down. 2. weak pull-up. 3. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output. pin description pin name description 1 ref input reference frequency, 5v-tolerant input 2 clkb1 [1] clock output, bank b 3 clkb2 [1] clock output, bank b 4v dd 3.3v supply 5 gnd ground 6 clkb3 [1] clock output, bank b 7 clkb4 [1] clock output, bank b 8s2 [2] select input, 5v-tolerant input 9s1 [2] select input, 5v-tolerant input 10 clka4 [1] clock output, bank a 11 clka3 [1] clock output, banka 12 gnd ground 13 v dd 3.3v supply 14 clka2 [1] clock output, bank a 15 clka1 [1] clock output, bank a 16 clkout [1] clock output, internal feedback on this pin table 1. select input decoding s2 s1 clock a1?a4 clock b1?b4 clkout [3] output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n
cy2309 a document #: 38-07378 rev. *b page 3 of 9 figure 1. ref. input to clka/clkb delay vs. difference in loading between clkout and clka/clkb
cy2309 a document #: 38-07378 rev. *b page 4 of 9 maximum ratings supply voltage to ground potential ............... ?0.5v to +7.0v dc input voltage (except ref, s2, s1) ..........................................?0.5v to v dd + 0.5v dc input voltage (ref, s1, s2) ....................... ?0.5v to 7.0v storage temperature .................................?65c to +150c junction temperature ................................................. 125c junction-to-ambient thermal resistance 16-pin tssop.......................................................... 115c/w static discharge voltage (per mil-std-883, method 3015) ............................ > 2000v this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). table 2. operating conditions for cy2309azc-xx commercial temperature devices parameter description min. max. unit v dd supply voltage 3.135 3.465 v t a operating temperature (ambient temperature) 0 70 c c in input capacitance 7pf t pu power-up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms table 3. electrical characteristics for cy2309azc-xx commercial temperature devices parameter description test conditions min. max. unit v il input low voltage cmos levels, 30% of v dd 0.25 v dd v ih input high voltage cmos levels, 70% of v dd 0.7 v dd i il input low current v in = 0v 50 a i ih input high current v in = v dd 10 a i ol output low current [4] , (?1) v ol = 0.5v 12 ma (?1h) 18 i oh output high current [4] , (?1) v oh = v dd ? 0.5v ?12 ma (?1h) ?18 i dds power-down supply current ref = 0v, s1 = v dd , s2 = v dd 50 a i dd supply current unloaded outputs @ 200 mhz 115 ma loaded outputs @ 200 mhz, c l = 10 pf 145 table 4. switching characteristics for cy2309azc-xx commercial temperature devices [5] parameter description test conditions min. typ. max. unit reference frequency 50 200 mhz reference edge rate 30% to 70% of v dd 0.5 4 v/ns reference duty cycle 25 75 % t 1 output frequency c l = 10 pf 50 200 mhz c l =15 pf 50 140 mhz duty cycle [4] = t 2 / t 1 measured at v dd / 2455055% t 3 rising edge rate [4] , (?1) 20% to 80% of v dd , c l = 15 pf 0.8 4 v/ns rising edge rate [4] , (?1h) 20% to 80% of v dd , c l = 15 pf 1 4 v/ns t 4 falling edge rate [4] , (?1) 80% to 20% of v dd , c l = 15 pf 0.8 4 v/ns falling edge rate [4] , (?1h) 80% to 20% of v dd , c l = 15 pf 1 4 v/ns notes: 4. parameter is guaranteed by design and characterization. not 100% tested in production. 5. all parameters specified with loaded outputs.
cy2309 a document #: 38-07378 rev. *b page 5 of 9 ttb total timing budget window [6] outputs @ 200 mhz, tracking skew not included 650 ps t 5 output to output skew [4] all outputs equally loaded 200 ps t 6 input to output skew (static phase error) [4] measured at v dd / 2, ref to clkout 250 ps t 7 device to device skew [4] measured at v dd / 2 500 ps t j cycle to cycle jitter [4] loaded outputs 200 ps 35 ps rms t lock pll lock time [4] stable power supply, valid clock at ref 1.0 ms table 5. operating conditions for cy2309a zi-xx industrial temperature devices parameter description min. max. unit v dd supply voltage 3.135 3.465 v t a operating temperature (amb ient temperature) ?40 85 c c in input capacitance 7pf t pu power-up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms table 6. electrical characteristics for cy2309azi-xx industrial temperature devices parameter description test conditions min. max. unit v il input low voltage cmos level, 30% of v dd 0.25 v dd v ih input high voltage cmos level, 70% of v dd 0.7 v dd i il input low current v in = 0v 50 a i ih input high current v in = v dd 10 a i ol output low current [4] , (?1) v ol = 0.5v 12 ma (?1h) 18 i oh output high current [4] ,(?1) v oh = v dd ? 0.5v ?12 ma (?1h) ?18 i dds power-down supply current ref = 0v s1 = v dd , s2 = v dd 50 a i dd supply current unloaded outputs @ 133 mhz 80 ma loaded outputs @ 133 mhz, c l = 10 pf 110 table 7. switching characteristics for cy2309azi?1 industrial temperature devices [5] parameter name test conditions min. typ. max. unit reference frequency 50 133 mhz reference edge rate 30% to 70% of v dd 0.5 4 v/ns reference duty cycle 25 75 % t 1 output frequency c l = 15 pf 50 133 mhz duty cycle [4] = t 2 / t 1 measured at vdd / 2 40.0 50.0 60.0 % t 3 rising edge rate [4] , (?1) 20% to 80% of v dd , c l = 15 pf 0.5 3 v/ns rising edge rate [4] , (?1h) 20% to 80% of v dd , c l = 15 pf 0.8 4 v/ns t 4 falling edge rate [4] , (?1) 80% to 20% of v dd , c l = 15 pf 0.5 3 v/ns falling edge rate [4] , (?1h) 80% to 20% of v dd , c l = 15 pf 0.8 4 v/ns ttb total timing budget window [6] outputs @ 133 mhz, tracking skew not included 650 ps note: 6. ttb is the window between the earliest and the latest output clocks with respect to the input reference clock across variatio ns in output frequency, supply voltage, operating temperature, input clock edge rate, and process. the measurements are taken with the ac test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error.ttb will be equal to or smaller than the maximum specified value at a given o utput frequency. table 4. switching characteristics for cy2309azc-xx commercial temperature devices [5] (continued) parameter description test conditions min. typ. max. unit
cy2309 a document #: 38-07378 rev. *b page 6 of 9 t 5 output to output skew [4] all outputs equally loaded 200 ps t 6 input to output skew (static phase error) [4] measured at v dd / 2, ref to clkout 250 ps t 7 device to device skew [4] measured at v dd / 2 500 ps t j cycle to cycle jitter [4] loaded outputs 200 ps 35 ps rms t lock pll lock time [4] stable power supply, valid clock at ref 1.0 ms switching waveforms table 7. switching characteristics for cy2309azi?1 industrial temperature devices [5] parameter name test conditions min. typ. max. unit duty cycle timing t 1 t 2 v dd /2 v dd /2 v dd /2 all outputs rise/fall time output t 3 vdd 0v 20% 80% 80% 20% t 4 output-output skew v dd /2 v dd /2 t 5 output output input-output propagation delay v dd /2 t 6 input output v dd /2
cy2309 a document #: 38-07378 rev. *b page 7 of 9 test circuits switching waveforms (continued) v dd /2 v dd /2 t 7 clkout, device 1 clkout, device 2 device-device skew ordering information ordering code package type operating range cy2309azc?1 16-pin 4.4-mm tssop commercial, 0c to 70c cy2309azc?1t 16-pin 4.4-mm tssop ? tape and reel commercial, 0c to 70c cy2309azc?1h 16-pin 4.4-mm tssop commercial, 0c to 70c cy2309azc?1ht 16-pin 4.4-mm tssop ? tape and reel commercial, 0c to 70c cy2309azi?1 16-pin 4.4-mm tssop industrial, ?40c to 85c cy2309azi?1t 16-pin 4.4-mm tssop ? tape and reel industrial, ?40c to 85c cy2309azi?1h 16-pin 4.4-mm tssop industrial, ?40c to 85c cy2309azi?1ht 16-pin 4.4-mm tssop ? tape and reel industrial, ?40c to 85c 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd
cy2309 a document #: 38-07378 rev. *b page 8 of 9 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimensions total timing budget, ttb, and spread aware are trademarks of cy press semiconductor. all product or company names mentioned in this document may be the trademarks of their respective holders. 16-pin thin shrunk small outline package (4.40-mm body) z16 51-85091-**
cy2309 a document #: 38-07378 rev. *b page 9 of 9 document history page document title: cy2309a, nine-output, 200-mhz zero delay buffer document number: 38-07378 rev. ecn no. issue date orig. of change description of change ** 115507 08/19/02 ctk new data sheet *a 121893 12/14/02 rbi power-up requirements added to operating conditions *b 124598 03/06/03 rgl changed v il max. value in commercial temp. device from 0.3v to 0.25v changed i dd max. values in commercial temp. device from 75 and 150 to 115 and 145 ma, respectively change v il max. value in industrial temp. device from 0.3v to 0.25v changed i dd max.values in industrial temp. device from 60 and 120 ma to 80 and 110 ma removed preliminary (final data sheet)
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